The present invention is in the field of integrated circuit testing. More particularly it relates to methods for implementing CrossCheck integrated circuit testing structures and the apparatus resulting therefrom.
U.S. Pat. No. 4,749,947, issued on June 7, 1988 to T. Gheewala describes a grid-based CrossCheck testing structure for testing integrated circuits. The specification of that patent is incorporated herein in its entirety. The CrossCheck testing structure is a specific type of storage-free matrix structure suited to testing a large class of randomly addressable combinatorial and like digital logic circuits in large-scale integrated form. The CrossCheck testing structure may be implemented using any of several common methods used to fabricate integrated circuits. Several implementations of the test structure using different technologies are schematically illustrated in the '947 patent. These implementations comprise a sense transistor coupled both to a sense line and a point being probed electrically. The '947 patent does not show how the CrossCheck testing structure can be implemented in an area-efficient manner on an integrated circuit.